1. Field of the Invention
The present invention relates to a fabrication method for a chip package, especially to a fabrication method for a high pin count chip package.
2. Description of the Prior Art
Electrical products with compact sizes have been a demanding trend for customers with improvement in technology. While the performance of integrated circuit keeps improving, the integrated circuit carriers also need improved.
QFN (Quad Flat Non-lead) package, a package technology using lead frames, is now more popular because of its lower e-parasitic effects, thermal resistance and less package size and weight without fewer components. The conventional QFN lead frame adopts single-row lead pins and is not sufficient for usage since customers have expected higher pin count and high density lead frame design.